Field of the Invention
The present invention relates to semiconductor devices, such as transistors, specifically, field effect transistors (FETs), and, more particularly, to a new process for preparing contacts for such devices, resulting in a novel, planarized, completely selfaligned structure.
The LOCOS (local oxidation of silicon) process for fabricating MOS (metal-oxide semiconductor) devices, especially CMOS (complementary MOS) is well-known and widely practiced throughout the semiconductor industry. It is a suitable process for design geometries greater than about 1 .mu.m feature size.
However, as feature sizes are reduced to sub-micrometer dimensions to achieve higher packing densities of devices, several problems emerge.
First, the depth of focus of the lithography stepper becomes smaller. Thus, the different heights of different features generate a depth of field problem.
Second, the spacing of contacts to the polysilicon gate and to the field oxide becomes critical at smaller dimensions. It will be appreciated that due to the use of separate alignment steps, the margin of error in aligning the contact can, if not adequate, result in either (a) etching through the field oxide, with consequent shorting of the silicon substrate to the diffusion source or drain region by the contact, or (b) contacting the polysilicon gate, with consequent shorting of the gate to the source or drain contact.
Such misalignments are accommodated by allowing a substantial space between source, drain and gate and between source, drain and field edge. As a result, high packing density is sacrificed.
Another requirement of the present processing scheme is that the gate contact is made to an interconnect which extends at right angle to the source-gate-drain line. Such a contact requires considerably more area than a contact directly down to the gate. However, the use of separate alignments dictate the present processing scheme, in order to avoid potential misalignment problems.
Finally, a problem well-known in the art with the LOCOS process is the so-called "bird's beak" problem, which occurs where the field oxide tapers to the substrate in the source and drain regions. Such a taper results in an electrical width smaller than the mask dimensions.
It is evident that the profusion of different heights during processing and the several alignment steps prevent efficient use of advanced lithography processes and other processes to generate high packing densities of devices on a substrate, since the depth of field reduces with the smaller dimensions that are needed for scaling.